MICRO TASKS AND SEQUENCES FOR CHARGE SHUFFLING READOUT (CSR)

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J R Barton

BRIEF DESCRIPTION OF CSR

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The charge shuffling readout mode enables the astronomer to build up a CCD

exposure comprising several on-chip charge movements made generally into and

out of an aperture of a masked CCD. A change of state of an external device

(etalon, filter wheel, polariser, telescope position, chopping secondary, etc)

and the operation of a shutter may be synchronised to these charge shuffling

movements. Alternatively, no mask may be used, resulting in superimposed images

from each of the phases, these images being separated spatially by the vertical

shuffling.

The object of charge shuffling is to attempt to improve the signal to noise

(S/N) of the observation by rapidly chopping between two states within the

timescale of some interfering observational variation. In addition, the object

may be to use the same part of the CCD to detect both states of the measurement

in order to provide better subtraction when, previously, the S/N may have been

limited by detector inconsistencies.

The ext device must be able to be programmed and initialised in such a way that

a series of sync pulses from the CCD controller will cause the ext device to

cycle through a known and predetermined sequence of conditions corresponding to

each shift of the charge on the CCD.

A choice between shuttered or unshuttered exposures is available. A shuttered

exposure enables unsmeared exposures to be made. However the shortest opening

times and maximum repetition rates (max may be 10Hz for physically small

shutters) of the particular shutter being used and even perhaps how rapidly the

shutter might wear out may limit phase times to relatively long values.

Unshuttered exposures open the shutter at the start of the exposure and close

it at the end just before the CCD is read out. These exposures offer the phase

times that may be very short (less than a millisecond) but may suffer from

objectionable image smearing, depending on the how rapidly the CCD charge

shifting occurs (CCD dependant) and how much of the phase or cycle time is

taken in moving the charge.

A cycle is constructed from a number of phase definitions and a repetition

feature in these enables more complex and lengthy cycles to be more easily

defined. Exposures may range in complexity from the simplest two-image shuffle

of comprising only 2 phases per cycle, through to a large number of image

phases each comprising a chopping between two conditions. A very fast flash

facility which fills the CCD in a single burst over a short interval is also

available to, for example, sample transient phenomena, eg occultations at less

than 1ms rates, if required.

In all CSR modes, it will be possible to prevent the shutter opening to produce

a dark frame so that the dark current or the incidence of cosmic rays may be

examined or recorded to subtract from the object measurements. Similarly, with

EXPTM and TINCR set to minimum values of 2 and TINCRmin respectively, a bias

frame can be generated permitting the electronic bias level and the level of

shift induced charge, etc to be determined.

 

DEFINITIONS

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The CSR requires the following to be defined. To the astronomer these would

ultimately be presented as a definition table that is able to be changed at

will. To the CCD controller they will be passed from the VAX as a series of

command lines...

 

INITIAL TIMING AND DELAY SPEC

Initially the VAX will do no timing checks. Timing restrictions will be taken

into account when when constructing the phase definitions and the cs command

during the "experimental" stage of the CSR project, i.e.

- which shutter is in use and the opening, Tdsho, and closing, Tdshc, times

are reflected in the phase period and EXPTM values.

- EXT device's time to settle, TDEXT, is needed and is sent as part of the cs

command in the "experimental" stage of the CSR project.

- other delays, eg micro processing times per phase, extra processing time

per cycle, time to get started, Tmargin, etc are also reflected in the phase

period and EXPTM values. in the "experimental" stage of the project

 

ULTIMATELY CONSIDER

Shutter definition (a choice of a few, eg small, large Uniblitz, Taurus, RGO

spectr, UCLES, etc) each resulting in its own a delay to open, Tsho, and a

delay to close, Tshc, used in the interactive setting of EXPTM and TINCR (or

the phase timing from a SYNC source) done by the VAX. *** INITIALLY HAND CODED

INTO PHASE DEFINITIONS ***

External device definition (a choice of a few, eg etalon, polariser, chopping

secondary, filter wheel, telescope settling time, etc) each resulting in a

micro invoked delay to step 1, Tex1, delay to step 2, Tex2, delay to step 3,

Tex3, etc, that may be sent to the controller. These delays are used in the

interactive setting of EXPTM and TINCR (or the phase timing from a SYNC source)

by the VAX. Initially, there is a need for a delay, TDEXT to be sent to the

micro to cover the possibility that the EXT device takes longer to settle than

the N Vshifts take to do, in which case the opening of the shutter must be

delayed until TDEXT has expired.

All the micro processing delays and Tmargin delays that must be used by the VAX

are to be inputted and changed at any time to update the system....

 

SNThe total exposure time comprises the sum of the following times (as relevent

to the type of CSR)

The total exposure time comprises the sum of the following times (as relevent

to the type of CSR)

SYNC1 AND SYNC2 DETAILS

When the CSR is to use the SYNC1/2 inputs the following VAX inputs are needed:

1. Tsync-start for cs(n5) in seconds

2. PERIOD1 or 2 is the SYNC1 or 2 period (in seconds) needed if cs(n6) = 1 or

2 and should be entered by the astronomer to 6 dec places (i.e. 1us

precision)

 

PHASE DEFINITIONS

Each phase should be regarded as a "shift then expose" operation, done in that

order, with some attached conditions included in the phase definition. The

cycle definition comprises a number of phase definitions built up in a table.

Each phase definition is as follows (parameters to be quickly skipped ensuring

high speed on non-shuttered phases and long decodes done only on the slower

shuttered phases in the CSR):

Px STPH, ACTIR, EXPTM, TINCR, UP, NVSHIFT, REPEATS, OFFSET

where Px = PS for a start-up phase

= PR for a running phase

= PE for an end-up phase

NB: The phase table must begin with a PI which initialises the new

phase table, and end with a PT which terminates the phase table. Ultimately

these may be inserted automatically by the VAX but initially they may need to

be entered manually as part of the phase table.

STPH = interrupt used to start next phase

*** THIS PARAMETER IS ALWAYS SET TO ZERO IN THE EXPERIMENTAL STAGE OF THE

PROJECT ***

= 0 skip, I/R as set in cs command

= 1 SYNC1

= 2 SYNC2

= 3 TINCR

= 4 N.V.Shift

= 5 EXPTM

= 6 skip wait, no I/R set, don't set wait for next I/R flag

ACTIR = action to be taken immed after phase start I/R

=-1 enable trigger EXT device, set EXTFLAG and ACTIONFLAG

= 0 no action, skip leaving ACTIONFLAG clear

= 1 open shutter set ACTIONFLAG (for non-shuttered open)

= 2 close shutter set ACTIONFLAG (for non-shuttered close)

EXPTM = for use with shuttered phases

= 0 repeat the already loaded EXPTM, set sh. open flag

= 1 disable EXPTM-timed shutter opening this phase

>= 2 load number into EXPTM counter and set a shutter open

flag

NB: Unsigned number, max value of EXPTM is 2^16-1

TINCR = 0 ignore, skip, repeats last TINCR

= 1

>= 2 load the number into the TINCR counter

NB: Unsigned number, max value of TINCR is 2^16-1

UP = 0 skip, ignore, don't change direction

= 1 shift up, forward or + direction, toward readout reg

=-1 shift down, reverse or - direction, away from RO reg

NVSHIFT = 0 repeat already loaded Vshifts (1 or >=2), set VSFLAG

=-1 do no Vshifts this phase, clear VSFLAG

= 1 do one Vshift, set WC6 bit-0, and set VSFLAG

>= 2 load the number into the N.V.SHIFT counter, set WC6

bit-1, and set VSFLAG

NB: Signed number, NVSHIFT has a max value of 2^15-1

REPEAT = 0 ignore, skip, no repeats required

>= 1 do this number of repeats

OFFSET = 0 ignore, repeat the same PXn if REPEAT >=1

>= 1 is the offset to be subtracted off the current phase

number to get to the phase number of the start

of the repeat

Extra parameters to allow extension of the Px command for a more complex run

specification may be added in the future (or do we invent another command....)

 

THE PHASE TABLE

Cycle Definition: a set of running phase definitions, executed in the running

sequence, that can be repeated.

The phase definition has built into it a repeat line function so that a phase

can be repeated a number of times. This will save lots of memory space and time

in making some run definitions. Also, may want to repeat, say, a pair of lines

a number of times so that the repeat function uses an offset to find the phase

number (always a lower phase number) from which the repeat should start.

The cycle definition table is sent to the CCD controller as a series of Px

commands one for each line of the table.

The downloading of the Phase Table entries must be preceded by sending the 'PI'

command, which initialises the new Phase Table. Following the downloading of

the Phase Table entries, the 'PT' command must be sent, which terminates the

Phase Table.

Phase Table Definition Rules:

- the first phase table definition of any type (START, RUN or END), is not

offsetable, i.e. cannot loop back.

- phase definitions defined within a repeat loop are themselves not repeatable

(i.e. no nested repeats or loops).

- a phase definition in which the offset is > 0 must have a repeat count > 0.

- the minimum number of cycles is 1; a cycle count of zero will result in

inconsistent behaviour.

- the maximum number of phase table entries (including start, run and end

phases) is 256.

- phase table entries must be made (i.e. downloaded) in order, i.e.

START phases, followed by RUN phases, followed by END phases.

- negative numbers for phase table entries need to be entered as 16-bit

unsigned decimal 2's complement equivalents, (e.g. -1 will be entered as 65535,

-2 as 65534, etc).

NB: There is an important difference between the description of the Startup,

Running and Endup sequences in thiss document and the implementation in the

micro software. This is that the microcode makes no distinction in the

processing of START, RUN and END phases. The only case where the type of phase

is checked is if the 'sp' command is received, at the end of the current phase,

a check is made to see if END phases are currently being executed, and if not

to see if there are any END phases.

 

THE "CS" COMMAND

The charge shuffling readout cs command is to be the last command sent by the

VAX and its functions are to send the final details of the exposure and to

trigger the start of the CSR. The cs command is -

cs n1, n2, n3, n4, n5, n6, n7, contr

where n1 = number of cycles (1 to 65535)

n2 = selects the C14 MMR, setting the TINCR and EXPTM clock rate

= 0 loads C1B0 for max TINCR of < 65ms ................ 1us

= 1 loads C1C0 for max TINCR between 65 and 650ms...... 10us

= 2 loads C1D0 for max TINCR between 650ms and 6.5 sec. 100us

= 3 loads C1E0 for max TINCR between 6.5 and 65 sec.... 1ms

= 4 loads C1F0 for max TINCR between 65 and 650 sec.... 10ms

n3 = minimum phase time for BFs, TINCRmin, loaded into TINCR

counter. Value is appropriate to the selected clock rate

represented by n2 above.

n4 = TDEXT time to be loaded into the TDEXT counter, i.e. the

comandeered N.VS CNTR. Value is appropriate to the selected

clock rate represented by n2 above.

n5 = start of exposure triggered by....

= 0 start immediately, don't wait for an I/R

= 1 by SYNC 1 I/R (hardware start of the exposure)

= 2 by SYNC 2 I/R (hardware start of the exposure)

n6 = all phases triggered by .....

= 0 ignore and use the Px specification

= 1 SYNC 1 I/R (hardware start of each phase)

= 2 SYNC 2 I/R (hardware start of each phase)

= 3 TINCR I/R (soft software start of each phase)

NB: The SYNC signal used to start and/or stop the exposure

must not be the one that triggers all running phases

n7 = stop the exposure triggered by....

= 0 nothing extra, ie use cycle counter or sc command

= 1 by SYNC 1 I/R (hardware stop of the exposure)

= 2 by SYNC 2 I/R (hardware stop of the exposure)

contr = control byte (in hex) containing

bit 0 = required state of EN SHUTTER OPEN (bit 0 in

WC4) for the duration of the CSR,

bit 1 = required state of EO EXPTM CLOSES SHUTTER

(bit 1 in WC4) for the duration of the CSR,

bit 2 = set if BF to be done (DF and NP are determined

by the bit 0 and bit 1 states) and must be cleared or ignored if NP being done,

i.e. bit 0 is set

bits 3-7 for future expansion of control word

Bits 0 to 2 of the control word are to be set by the VAX from astronomer

input. Bits 0 and 1 must be set into the bits 0 and 1 respectively of the WC4

write control register. They replace the downloaded state of these bits the

state of which should be saved before being overwritten so that they may be

restored at the completion of the CSR. The micro will interpret the three bits

as follows -

Astronomer Request Control uP Interpretation - write the

bit 2 bit 1 bit 0 control bits to WC4 and

C DO A EO EXPTM EN SH.

O BF CLOSES OPEN

D Shutter open SHUTTER

E continuously mode (unshuttered phase)

1 - Normal exp (NP) 0 0 1 disarm EXPTM, use START/STOP EXP to open

shutter at start and close at end of exp

0 - Dark frame (DF) 0 0 0 disarm EXPTM, use ST/ST EXP ineffective.

sh. stays closed. phase timing as for NP

4 - Bias frame (BF) 1 0 0 disarm EXPTM, use ST/ST EXP ineffective.

sh. stays closed. Use TINCRmim.

Shutter opened and

closed each phase (shuttered phase)

3 - Normal exp (NP) 0 1 1 EXPTM used, START EXP used each phase

2 - Dark frame (DF) 0 1 0 EXPTM used, START EXP used each phase

EXPTM and phase times as for NP

6 - Bias frame (BF) 1 1 0 EXPTM used, START EXP used each phase

EXPTM set = 2. Use TINCRmin

The times for "Phase timing MINIMISED" will ultimately be computed by the VAX

and are passed to the micro in the cs command parameter n3, TINCRmin. For the

bias frames, set a BIASFLAG, whereapon the micro must override the phase

definition's values of the TINCR counter value with TINCRmin and set the EXPTM

values to 2 for the shuttered BF. There may be a problem with getting short

phase times for a BF when hardware inputs SYNC1/2 are used to trigger phases or

cycles. In this case the appropriate DF may have to do the job of the BF.....

 

STATUS, ABORT and STOP COMMANDS

The following VAX read status commands have been created to facilitate

debugging the hardware and software. In order to preserve the timing of the CSR

command the VAX may be prevented from issuing these commands once the cs

command has been sent. The read status commands applicable to the CSR are -

xs Exposure status, returning the status of the exposure as

follows

0 = idle status where the hardware is in STBYM

1 = setting-up status of the CSR is underway

2 = start-up sequence of the CSR is underway

3 = running sequence is set just before the first phase

definition is executed, ie the first start phase, PS, and

remains set till last PE has completed. Thus, it does not

reflect the PS, PR and PE conditions

4 = end-up status is set after the completion of the last

phase definition

5 = wrap-up status is set after the completion of the wrapup

sequence

0 = idle state, set after wrap-up when the exposure completes

and the hardware is back in STBYM ready for the normal

readout

 

pc Phase count, returns the number of phases remaining to be

executed. This is the TOTAL number of phases, taking into account repeated

phases, number of cycles, offset repeated phases etc. This is the actual

counter that the microprocessor uses to control phase execution. This command

is in general of more use than the 'cc' command.

cc Cycle count returning the current (decrementing) cycle

count of the CSR

Abort Commands applicable to the CSR and issued when the exposure is to be

aborted with no saving of any accrued data are -

ai Abort immediately. As soon as possible drops out of the

current CSR, does the wrap-up without executing any further phases, and awaits

an 'IN' command from the VAX to reload the VAX downloaded parameters and get

into STBYM (thus cleaning out the CCD), and making itself ready for the

specific parameters relating to the next CSR exposure. Cleans up any CSR states

from the aborted run (alternatively, new runs always overwrite parameters that

may have been left over from aborted runs)

Stop command applicable to the CSR and issued to prematurely stop the

exposure with a readout of the accrued data is:

sc Stop at the end of the current cycle

The micro on detecting an sc command should process this as rapidly as possible

by merely setting a flag STOPFLAG which will be tested at the end of each CSR

cycle and during the CYCLETEST part of forecasting the next phase. Flag set

will then cause the CSR to go to end-up sequence irrespective of the current

cycle count. The current cycle count should be saved for reading by the VAX.

 

INHIBIT VAX COMMANDS DURING EXPOSURE

The ability to perform all the VAX commands is essential for debugging purposes

but clearly there are some exposure modes where these commands would get in the

way.

In nonshuttered exposures, where the phase timing, eg TINCR, determines the

exposure, and in critically timed shuttered exposures (with a need for

sample-time precision), the VAX status requests and TEL commands should be

turned off. Otherwise, there will be a serious jitter problem (as found in the

TSR) in the TINCR operation due to these commands being processed by the micro

and holding up the start of a cycle. In TSR these commands were removed from

non-shuttered TSRs and for shuttered use, I think???

In shuttered exposures (where the exposure time is accurately and unchangeably

set by hardware counters) and where delays opening the shutter, as the CSR

progresses, may be tolerable, the VAX status and TEL commands could be

permitted. Thus, very long exposures could be monitored.

A simple facility should be available in the VAX for turning on and off the

VAX's ability to interrogate the micro during the exposure. If one could

selectively bring up permitted VAX commands it would even be more useful, eg,

permit st, permit both st and cc, permit st, cc and TEL, etc.....

 

CSR EXPOSURE TIMES

Since the VAX may not be allowed to poll the micro to determine the progress of

the CSR it needs to be able to determine how long the CSR exposure will take so

that polling may start once the exposure is completed. The method of

calculating this time is described in a separate document "COMPUTING THE CSR

EXPOSURE TIMES". The document also describes how the exposure times are

shortened when the exposure is either stopped prematurely or aborted.

 

GENERAL REQUIREMENTS AND DISCUSSION

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- the VAX should send the cs command only if the CCD controller is in STBYM

- In order to accurately generate short TINCR and EXPTM and TDEXT intervals and

to provide greater resolution in the timing, the clocking frequency applied to

the TINCR, EXPTM and the commandeered N.VS CNTR counters is altered. This is

done by a software reconfiguration of of the counter chip at card location C14

to change the scaler output frequency, FOUT. FOUT of card C14 drives the TINCR

clock directly. The clock source for the EXPTM counter is changed to use CK3

(SRC3) of counter chip C24 (see below). The MMR of C14 is also changed to

deselect comparator function for counter 1 now used as the TDEXT counter,

reflected in the last hex digit being set to 0.

MAX TINCR TIME FREQ SCALER FREQU RESOLUTION COUNTER C14 cs TINCR

REQUESTED OUTPUT MAX TIMING MMR (hex) command start

ERROR n2 value

up to 65 ms F1 1 MHz 1 us C1B0 0 20000

from 65 to 650 ms F2 100 kHz 10 us C1C0 1 2000

from 650 to 6.5 sec F3 10 kHz 100 us C1D0 2 200

from 6.5 to 65 sec F4 1 kHz 1 ms C1E0 3 20

from 65 to 650 sec F5 100 Hz 10 ms C1F0 4 3

- the operating mode of the TINCR counter is mode Q with a CMR of hex 92A1 (the

ROM default value) which defines

- active high level gate 2 operation

- count on falling edge of CK2 (SRC2)

- enable hardware retrigger off gate edge w/ [count]-->[hold]

- reload from load register at ea TC

- count repetitively

- binary count

- count down

- active high TC pulse

The LOAD register of this counter is loaded on the fly with the value required

for the next phase. The new value is loaded into the counter at the TC. I

suspect the desired value of TINCR should be loaded, i.e. not value-1, and that

a software step is not needed (indeed probably can't be done anyway).

- the MMR of counter card C24 needs to be changed from the normal CCD readout

default value of hex C1DC to hex C1D8 (same as that used in TSR) in order to

deselect the alarm comparator output on the EXPTM counter.

- the operating mode of the EXPTM counter is mode E (rather than the default

mode R and the hex '5125' for TSR) with a CMR of hex 5325 which defines

- active high level gate 2 operation

- count on falling edge of CK3 (SRC3)

- disable special gate

- reload from load register at ea TC

- count repetitively

- binary count

- count down

- active low TC pulse

The LOAD register of this counter is loaded on the fly with the value required

for the next phase. The new value is loaded into the counter at the TC. I

suspect the desired value of EXPTM should be loaded, i.e. not value-1, and that

a software step is not needed (indeed probably can't be done anyway).

- The N.VS CNTR, counter 1 in C14 is to be commandeered for use in timing the

TDEXT delay. This is needed only for shuttered CSR exposures and should not be

used on non-shuttered exposures in order to keep the cycle times as short as

possible.

The MMR of C14, changed above for the FOUT clock, has also been changed to

disable the comparator function for counter 1. Thus the MMR last hex digit

changes from 4 to 0. The CMR of counter 1 will also be changed from hex D1AD

to hex D225 for mode F operation of the TDEXT counter - the high state of the

output and a low going TC being retained. Thus, TDEXT counter definition is

- active high edge triggered using gate 1

- count on falling edge of CK2 (SRC2)

- disable special gate

- reload from load register at ea TC

- count repetitively

- binary count

- count down

- active low TC pulse

This use of N.VS CNTR as the TDEXT counter is acceptable as there is no mode

change within the CSR. Note that the counter TC clocks a flip-flop that must be

hardware reset (this same reset may also edge trigger the counter) and there

are several sources able to do this.

NB. That if the EXT device is slow to operate compared with the Vshift time

then Tmargin may have to be increased to ensure the EXT device has settled for

a reasonable time before the end of the phase otherwise the exposure will be

done with a non-settled EXT. VAX must sort this out as it determines the

minimum TINCR time or phase trigger period but, initially, this will be hand

coded into the phase definitions.

The TDEXT counter is used by loading the TDEXT time into the load register,

loading the counter and stepping the counter in set-up sequence. In running

stage, the micro sends a !TRIG VS CNTR pulse (WP2,1) and can set up the PIA for

the I/R or to poll for "VS CNTR TC" to indicate that the TDEXT counter has

timed out.

- an ENABLE CSR selective set/clear flip=flop, EN CSR, has been provided to

enable the generation of V clocks in the WAIT mode condition that exists for

the duration of the CSR exposure time. V clocks are normally prevented in WAITM

during the EXPTM phase of standard CCD imaging. EN CSR should be set

immediately after entering WAITM in the set-up sequence and it should be

cleared in the wrap-up sequence just after the saved parameters have been

reloaded to return the controller to normal and just before the loop is

re-started.

- normal readout of the CCD will also include the standard double windowing and

horizontal and/or vertical binning facilities (including split binning) as

defined by the standard OBSERVER CCD window facilities.

- the VAX should ensure that the required time to perform EXPTM + VSHIFTS +

computing time + delays fits within the TINCR time..... Refer to the document

"Computing the CSR Readout Exposure Times" but in the experimental stage of the

project these will be hand coded into the phase definitions.

- once the VAX issues the cs command only an abort or a premature stop will

affect the readout (hold, extend and continue will not be possible)

- PTE (prepare to expose) sets up a non-standard configuration of stopped

vertical clocks (high or low state) during exposure to establish under which

electrodes the photocharge is accumulated. This is required to reduce defects,

dark currents, hot top rows, etc. Fractional pixel shifts of the centre of the

pixel are also provided with this facility. Some CCDs have PTE enabled by the

downloaded parameter tables (bit 5 set of WC4) and the CCDs performance has

been optimised using it.

This facility is retained in full in CSR for three phase CCDs (all current AAT

CCDs except Thomson). However, it is only partially available with four phase

CCDs (Thomson CCD only) as there are complications in providing a glitch-free

reversal of the vertical clocks as only three of the four phases are able to be

switched.

For the Thomson CCD, as a temporary experiment, the following must be done in

order to both reverse the clocks and to do the limited PTE (a single stop

midway in V shift sequence):

- hardware swap PhiV4 and PhiV1 on the electronics box dewar connector

- generate a (set of) new SPEED files for Thomson, red and/or blue CCD, with

the timing of PhiV4 and 1 reversed, i.e.

V1 8,9,14,9,5,15,24,3 changed to V1 2,9,14,9,5,15,24,3

MC 2,9,5,15,7,6,7,6 changed to MC 8,9,5,15,7,6,7,6

These changes route PhiV2 and 4 through the reversing network and whenever

these two phases are high, either at the end of a full V shift triplet or

at the PTE condition when PTE is enabled and with

VS 3,10,30 changed to VS 12,10,30

they may be swapped so that subsequent

clocking will be reversed.

The state of the V clocks at the PTE condition and the correct WC7 command to

use to reverse the V clocking direction is established in the CSR set-up

sequence as described below. Thereafter, the first V shift of a CSR phase

takes the V clocks out of the PTE condition and sequences them through to the

non-PTE state found at the end of a normal vertical clock triplet. This

return to the normal state is counted as one vertical shift. After the required

number of vertical shifts for the CSR phase has been completed the micro

will invoke an immediate shift to the PTE condition. This last action is NOT

counted as a vertical shift.

Whether or not the WC4 bit-5 (EN PTE ON SHUTTER OPEN) has been set and for all

the possibilities of PTE, to change the vertical clock direction from the

reversed condition to the forward direction the command WC7,1 must be issued.

Sending WC7,1 will always ensure the vertical clocks are returned to a forward

direction. However, the success of the direction change (wrt preserving the CCD

image) relies on the clock phase swopping (that is done to get back to forward

direction) involving two clocks that are in the same hi or lo state. This will

be the case if an integer number of vertical shifts have been done in the

reverse direction.

If the EXPTM counter is not going to be used as in shutter open continuously

mode the micro will need to test the EN. PTE ON SHUTTER OPEN bit in WC4 and,

if found set, the micro should set bit 3 of all WC6 bytes written during the

TSR. In practice, this can be done even if EXPTM is used as the hardware will

look after the cases of PTE being set from the two sources (START EXP pulse or

the micro triggered PTE).

- apart from sending WC6,10 to establish the state of the V clocks at the PTE

condition, described above, there are two possible WC6 commands that may be

sent in the running sequence:

- if NVSHIFTnext, the number of vertical shifts to be done in the next

phase, is only one then the N.V.SHIFT counter is not used and, instead, WC6 bit

0 is set (along with bit 3, as described above, if PTE is required) with all

other bits of the WC6 byte cleared.

- if NVSHIFTnext is 2 or more then the N.V.SHIFT counter is used (and must

be so loaded) and WC6 bit 1 is now set (along with bit 3, as described above,

if PTE is required) with all other bits of the WC6 byte cleared.

- the PhiVEXP function will also be preserved with CSR exposures and is

activated if EN PhiV EXP bit-3 of WC4 is set. This causes the voltages applied

to the CCD during exposure times (i.e. when not vertically shifting) to be set

to more favourable levels to suppress dark currents, light emitting defects,

etc. During vertical shifts, the voltages applied may be increased to improve

the charge transfer characteristics. If this function is enabled in the normal

downloaded parameters the CCD will have been characterised under these

conditions, thus it is important to retain this facility in the CSR. This is

retained by the micro ensuring that all writes to WC4 contain this bit set.

- the stopped state high/low condition [[[or the running state (NO - NOT THE

RUNNING STATE: THE LOOP WILL NOT RUN WITH THE EN FULL uP VSC BIT SET AS IT IS

BLOCKED BY ENHWVS BEING FALSE ON SHEET 9/ELS40)]]] of the H and R electrodes

during an exposure will be unchanged when doing the CSR and will be left as

required by the downloaded parameters for the particular CCD being used. and

this condition will not be changed by doing the CSR. Under uP FULL VSC, a

cleared state of the uP VS BUSY flag invokes both PhiV EXP and PhiHR EXP if

these conditions are enabled in the download. Thus if the micro is not busy V

shifting then hardware sets these EXP conditions as required.

- some of the micro commands to the hardware require the new condition to be

OR'd into the existing condition, eg the WC4 and WC6 command.

- The conditions existing before the start of the CSR exposure (before any

changes are made) should be saved and used to restore the system to its pre-CSR

state once the CSR exposure has finished. This is necessary to ensure that the

CSR exposure remaining on the CCD is read out as expected, in the normal way,

using the CCD controller ROM default parameter tables as modified by subsequent

VAX downloaded parameter tables, speed and window files. Note that the pre-CSR

conditions cannot be restored by means of an RE. or IN. command as this process

temporarilly upsets the CCD clocks and would destroy the CSR generated image.

- some sort of TEL function is essential considering that normally the CCD is

interrogated regularly except during the CCD readout itself. The exposure times

with the cs command can become very long and under these conditions there is

both a great nead and plenty of time available to do the TEL. However there are

times when is should not be done.....

TEL should be done as per the TSR. TEL is done by the micro in shuttered

exposures but I don't think the VAX asks for the TEL data?? LGW's Micro Command

Summary says in TSR that acquisition done only while the shutter is open and it

is disabled at all other times. In fact, TEL could be done after the last thing

in the setting up of the next phase providing that there was at least 200 or

300ms left to the next TINCR or SYNC1/2 I/R. VAX could determine this. Could be

a TEL enable bit in the cs command set if TEL can be done (no point in doing it

if VAX can't access it, thus may only be useful in shuttered exposures whose

timing is unaffected by micro delays.... ********* check this ******

- the lab HP360 should be able to implement the CSR

OPERATION

*********

The following sequence of operations is required to perform the charge

shuffling readout in response to the cs command. This description outlines the

sequence of events but not necessarily the order or the organisation of the

micro software.

 

SET-UP SEQUENCE

***************

- astronomer starts OBSERVER and calls for method "shuffle" which downloads the

charge shuffling micro-code.

- idle status, xs = 0, where the hardware is in STBYM, sent to the VAX on

demand

- astronomer selects, and the VAX downloads, the CSR "speed" table that is

appropriate to the CCD detector on the system. These will be the standard speed

tables currently in the system except for the Thomson CCDs which require a

small hardware mod and new speed tables (initially to be in JRBs account).

- astronomer loads the (standard) window containing the required windowing and

binning parameters for the readout of the CSR image.

- astronomer input, resulting in PI, PS, PR, PE, PT and the cs command, are

derived from:

- type of shutter and ext device parameters to be used

- type of run, eg normal, bias, dark, use of shutter

- the cycle spec in the form of a table of phase definitions

- required triggering modes, number of cycles, etc to be used

- disabling some VAX interrogation during exposure

- Ultimately, the VAX will test that the following timing conditions are met

before downloading the CSR paramters:

- Sigma time <= TINCR or SYNC1/2 I/R period

- Tdexs < TINCR(min)

<= TVshift?

>= TVshift?

- shutter maximum rates not exceeded and due allowance made for opening

and closing times

- VAX calculates and displays the total time of the exposure as it may not be

able to poll for a status report during the CSR exposure. If the astronomer

calls for a bias frame, the reduced EXPTM = 2 and minimum phase times, TINCRmin

(TINCR or SYNC1/2), must be taken into account in this exposure time

calculation. *** CAN THIS VAX CALCULATION BE AVOIDED IN THE EXPERIMENTAL STAGE

OF THE PROJECT ****

- the CSR exposure parameters (PI, PS, PR, PEand PT) are first sent by the VAX

and are stored away in micro RAM as required.

- finally the VAX sends the cs command with the last few run parameters and

this indicates that the exposure is to be started. The cs command is accepted

by the micro only if the controller is in STBYM.

- the cs command parameters are saved in RAM

- If requested by the astronomer, the VAX must avoid sending any further

commands (apart from STOP and ABORT commands) until the expiry of the

calculated exposure time. A subset, or all of the VAX commands may be sent on

some types of exposures.

- inhibit the hardware acquisition of TEL in this sequence

- setting-up status, xs = 1, sent to the VAX on demand

- Read and save the state of the following before any CSR action overwrites:

- C14 MMR

- C24 MMR

- TINCR CMR

- EXPTM CMR

- N.VS CNTR CMR

- WC1

- WC4

- WC6

- WC7

- test bit 5 of WC4 (EN. PTE ON SHUTTER OPEN bit). If set, arrange (by means of

a WC6 mask) that each write to WC6 has bit 3 set so that after each micro

triggered V shift the potentials on the V electrodes are left in the required

condition for exposing. If bit 5 of WC4 was not set, each write of WC6 should

have bit 3 clear.

- command the hardware to a clean stop (WC8,0), i.e. get the controller into

STOPM. This may take up to 10ms so do it first, go away and attend to other

setup tasks and check the status word for the STOPM condition later.

- set the EO EXPTM CLOSES SHUTTER and the EN SHUTTER OPEN bits in WC4 in

accordance with bits 1 and 0, respectively, of the control byte contained in

the cs command. This looks after DFs automatically by the EN SHUTTER OPEN bit

being cleared. If bit 2 is set, set the BIASFLAG to indicate that a BF is

required.

- change the EXPTM counter to mode E (rather than the default mode R) and

change it to use CK3 (SRC3) by loading its counter mode register with hex 5325.

Deselect the EXPTM alarm comparator output by loading the MMR of counter card

C24 with hex C1D8.

- the MMR of counter chip C14 is changed from C1E4 to the hex value found in n2

of the cs command in order to set the clock rate corresponding to the max TINCR

time required for the CSR.

- the CMR of the commandeered N.VS CNTR counter 1 of card C14 is changed from

hex D1AD to hex D225 for mode F counter TDEXT operation. Load TDEXT (n4 of the

cs command) into the counter load register, load the counter register and step

the counter.

- Set up for the most efficient running sequence operation. If possible all

processing should be optimised for minimum phase times for non-shuttered

exposures. Test the cs parameters and other relevant parameters and set up a

"run description" so that the "running sequence" software jumps straight to the

relevant action with a minimum of time delay. As much as possible pre-determine

all choices and options. For example:

- if using SYNC1/2 I/R then the TINCR field of the phase definitions can be

completely ignored.

- if the exposure is non-shuttered, the EXPTM field can be ignored

- initially skip the STPH field too

- needn't test OFFSET if REPEAT is zero

- don't use TDEXT delay (N.VS CNTR counter) in non-shuttered exposures

- test that the hardware is in STOPM (status_byte bits 0, 1 and 2 all zero).

Wait if not, in a hard loop. When in STOPM all hardware retriggering of the

loop V shift/H shift ceases.

- turn off fast scan, if it is on

- set the CCD clocks forward by writing WC7,1

- set EN FULL uP VSC bit in the set/reset byte. This disables the hardware

retriggering of V shifts and isolates the V counters so that they dont affect

the windowing and V binning.

- disarm XTRL/PPL counter and set its output high to force PhiVEN so that each

micro triggered vertical shift will result in a CCD shift without the first few

triggers being considered as extra lines (XTRL).

- the WC7,REVERSE command for the CCD in use can now be established by

performing the following sequence. Test (done via the WC6 mask that has been

set up earlier) if WC4 bit-5 has been set (EN PTE ON SHUTTER OPEN) in the

downloaded parameter table.

- IF SET

- write WC6,10 to set SHIFT TO PTE

- send TRIG.VSHIFT write pulse

- poll (hard loop) for end of uP VS BUSY using the PIA

- continue into IF NOT SET

- IF NOT SET

- read PhiV_byte

- if bits 0 and 1 same state, REVERSE = 2

- if bits 1 and 2 same state, REVERSE = 4

- if bits 0 and 2 same state, REVERSE = 8

- if all 3 bits same state, set REVERSE = 2

- set up to receive a stop or an abort (this condition is always the case and

no specific setup is done). An abort should, as soon as possible, cause a

drop-out from the CSR exposure, execute the wrap-up without executing any

further phases, and awaits an 'IN' command from the VAX to reload the VAX

downloaded parameters. A stop should probably set a STOPFLAG that is tested at

the end of a running sequence cycle.

- Get the controller from STOPM into WAITM and the loop restarted (NO: THE LOOP

WILL NOT RUN WITH THE EN FULL uP VSC BIT SET AS IT IS BLOCKED BY ENHWVS BEING

FALSE ON SHEET 9/ELS40) by requesting WAITR (WC8,01), then WC6,05 (complete one

V shift followed by a H readout) OR'd with bit 3 set if PTE required, followed

by a TRIG VSHIFT pulse. After the resulting shift of one row and its readout,

the system will be in WAITM. This may take about 10ms to complete. Completion

is indicated by the uPVS BUSY flag which can be polled from the PIA. It will be

set on the TRIG VSHIFT pulse and be reset at the end of the H readout.

- set the ENABLE CSR selective set/clear flip=flop, EN CSR, by writing to the

selective set register SS 80. This enables the generation of V clocks in the

WAIT mode condition that exists for the duration of the CSR exposure time.

- this ends the set-up sequence

 

START-UP SEQUENCE

*****************

- prepare for start-up according to n5 of the cs command, i.e.

- if n5 = 0 go immediately go to start-up sequence

- if n5 = 1 set up the PIA with EXT H/W SYNC 1 as the I/R source

- if n5 = 2 set up the PIA with EXT H/W SYNC 2 as the I/R source

- wait for I/R, process I/R then

- start-up status, xs = 2, sent to the VAX on demand

- determine, from n7 of the cs command, if SYNC1 or SYNC2 is to be activated

as a hardware stop of the exposure. Prepare the PIA for this possibility. In

the same way as done with the VAX "sc" command, an I/R received here should set

the STOPFLAG

- determine, from n6 of the cs command, the required source for the interrupts

that trigger the start of all running sequences phases and get into synch with

them:

(if n6 = 0 there may be more than one trigger source and this

triggering preparation should be ignored and, instead, the required phase

trigger as specified in PR phase definition's STPH field should be used

*** NOT IN EXPERIMENTAL STAGE ***)

if n6 is not = 0 AS IT WILL BE IN THE EXPERIMENTAL STAGE OF THE PROJECT,

then ALL phases are started by the same I/R and IT SHOULD BE ARRANGED THAT THE

PRn PHASE DEFINITION STPH SHOULD BE SKIPPED TO SAVE TIME DURING THE RUNNING

SEQUENCE

if n6 = 1 set up PIA for SYNC 1 and wait for next I/R

= 2 set up PIA for SYNC 2 and wait for next I/R

= 3 set up PIA for TINCR I/R, but first, get the TINCR

counter going by loading a short time of about 20ms. The value loaded is a

function of the TINCR counter clock frequency as set by the MMR loaded into

counter C14 from the cs command n2. A table of TINCR start values is accessed

as described above under the general requirements. While this is hapening...

- Wait for the first TINCR I/R.

- receive I/R and process it

- set up three phase pointer registers, CURRENT, PNEXT and FUTURE. At the

start of each phase, just after the interrupt, the contents of these three

registers are shuffled. Overwrite CURRENT phase number with PNEXT phase number

and overwrite PNEXT phase number with FUTURE phase number. Thus, in this new

phase, the CURRENT phase number is the PNEXT number that was set up in the last

phase and the new PNEXT number to be set up in this CURRENT phase is the

FUTURE phase as determined in the previous phase. Later, in this CURRENT

phase, the phase number to load into FUTURE will be determined after

examining the REPEAT and OFFSET parameters of PNEXT and examining the cycle

counter SCC, a REPEAT counter, and the STOPFLAG.

REFER TO: PSEUDO CODE FOR CHARGE SHUFFLING EXPOSURE RUNNING SEQUENCE - 18/9/95

LGW appended below, for further details of the microcode that actually

implements the running sequence.....

- the NEXT and FUTURE are then worked out

- *set up this

NB: for the EXPTM counter, in order to look after the first time thru AND

loading the counter when it is not counting (i.e. it is turned off for the

phase) first load the EXPTM into the load register, immediately test is EXPTM

(bit 5 of status_byte) is set. If not load the counter reg and step the

counter. If so, skip out.

- *forecast FUTURE

- micro sets running status here

- hit the hardware strobe R1 done here every phase

- wait for the selected I/R

[B] - receive I/R and process it

- *shuffle phase pointer registers

- *execute CURRENT phase as set up above

- *set up new PNEXT

- *forecast new FUTURE (the next entry in PS table or PR1 the

first entry representing the first phase of the cycle

described in the in the running definition table - we

could allow repeats here too just as in running

sequence)

- is PNEXT still a PSn?

- yes: stay in start-up sequence

- wait for the selected I/R

- loop to [B]

- no: go to running sequence is imminent

- wait for the selected I/R

- receive I/R and process it

- go immediately to running sequence

- if not, load PNEXT with PR1

- *set up PR1

- *forecast FUTURE

- wait for the selected I/R

- receive I/R and process it

- go immediately to running sequence

* refer to the running sequence for a complete definition of these actions

 

RUNNING SEQUENCE

****************

SUMMARY

[A] - receive the TINCR (or SYNC...) interrupt

- test if PNEXT=PE1: should we gone to end-up sequence?

if so, hop out to END2 to go the end-up sequence

if not, proceed...

- shuffle phase pointer registers

- execute CURRENT phase

- trigger EXT change if required (start timer, TDEXT, by

issuing a !TRIG VS CNTR pulse (WP2,1) to cover this,

but only if a shuttered CSR

- send TRIG VSHIFT to do the N Vshifts, fwd/bwd

direction, ending in a PTE as required

- wait for EO uP BUSY I/R OR end of TDEXT timeout

* - trigger the EXPTM if required

- test if PNEXT=0: no phase definition to set up

if so, hop out to END2

if not, proceed....

- set up PNEXT by

- load TINCR for next phase, if used, unless BIASFLAG

- load NVSHIFT or WC6 for next phase (and step counter?)

# - load WC7 direction byte for next phase

- determine if shutter is to open in next phase

* - load EXPTM for next phase, if used, unless BIASFLAG

NB: for the EXPTM counter, in order to look after the first time thru AND

loading the counter when it is not counting (i.e. it is turned off for the

phase) first load the EXPTM into the load register, immediately test is EXPTM

(bit 5 of status_byte) is set. If not load the counter reg and step the

counter. If so, skip out.

- determine if EXT is to change state in next phase

- forecast FUTURE phase (next, repeat or jump), cycle, test

STOPFLAG, or whether change of sequence or wrap-up

- hit the hardware strobe R1 done here every phase

- wait for next TINCR (or SYNC...) interrupt

- jump back to [A]

- END2:

- wait for next TINCR (or SYNC...) interrupt

- enter end-up sequence

# do this just on contents of PD, i.e. don't test whether changing is required

or not - just write out fwd WC6 or rev WC6 acc to the pD

 

 

- running status, xs = 3, sent to the VAX on demand

[A]- wait for the required TINCR or SYNC1/2 interrupt, receive and cancel

source.

- test if PNEXT=PE1: should we go to end-up sequence?

if so, hop out to END3 to quit running sequence

if not, stay in running sequence and continue.....

REFER TO: PSEUDO CODE FOR CHARGE SHUFFLING EXPOSURE RUNNING SEQUENCE - 18/9/95

LGW appended below, for further details of the microcode that actually

implements the running sequence.....

- SHUFFLE PHASE POINTER REGISTERS: overwrite CURRENT phase number with PNEXT

phase number and overwrite PNEXT phase number with FUTURE phase number.

Thus, in this new phase, the CURRENT phase number is the PNEXT number that was

set up in the last phase and the new PNEXT number to be set up in this CURRENT

phase is the FUTURE phase as determined in the previous phase. Later, in

this CURRENT phase, the phase number to load into FUTURE will be determined

after examining the REPEAT and OFFSET parameters of PNEXT and examining the

cycle counter SCC, a REPEAT counter, and the STOPFLAG.

- EXECUTE THE CURRENT PHASE, PCURRENT (triggering EXT and/or shutter, V Shifts,

and operate shutter) in the following order:

- trigger EXT change (if EXTFLAG and ACTIONFLAG set). Start TDEXT timer

by issuing a !TRIG VS CNTR pulse (WP2,1) to cover the time EXT takes, but only

if a shuttered CSR

- if ACTIONFLAG set and EXTFLAG clear, then issue a START EXP pulse to open

the shutter if ACTIRnext = 1 or issue a STOP EXP pulse to close shutter if

ACTIRnext = 2

- if VSFLAG is set

- send TRIG VSHIFT, to do the N Vshifts (N=1 or

>=2, shifting forward or backward and ending

in a PTE, as already set up in the set-up

PNEXT part of the phase)

- poll for EO uP BUSY

- then, if this is a shuttered CSR (and even if it is a DF), poll for "VS

CNTR TC" indicating that TDEXT has timed out

- send START EXP if the SHUTTER_OPEN flag is set (irresp. of DF or BF)

- clear the SHUTTER_OPEN flag

- test if PNEXT=0:

if so, hop out to END2 to quit running sequence

if not, stay in running sequence and continue.....

REFER TO: PSEUDO CODE FOR CHARGE SHUFFLING EXPOSURE RUNNING SEQUENCE - 18/9/95

LGW appended below, for further details of the microcode that actually

implements the running sequence.....

- SET UP PNEXT (set I/R, TINCR, N.V.SHIFT , direction, shutter use, EXT use for

the next phase):

- set up the interrupt used to start next phase, Pnext, by looking at the

STPHnext of Pnext's phase definition

if STPHnext = 0 skip and use I/R as set in cs command ** STPHNEXT = 0

ALWAYS DONE IN EXPERIMENTAL STAGE OF THE PROJECT ***

= 1 set up for SYNC1

= 2 set up for SYNC2

= 3 set up for TINCR

= 4 set up for N.V.Shift

= 5 set up for EXPTM

= 6 skip wait, no I/R set, set a NOWAIT flag

- if BIASFLAG not set, load TINCR for the next phase, Pnext, by looking at

the TINCRnext of Pnext's phase definition

if TINCRnext = 0 ignore, don't load, it will repeat last TINCR

= 1

>= 2 load TINCRnext into the TINCR counter

- if BIASFLAG is set, load TINCRmin (from cs command)

- load N.V.SHIFT for the next phase, Pnext, by looking at NVSHIFTnext of

Pnext's phase definition

if NVSHIFTnext = 0 repeat previous V.Shift set-up, set VSFLAG

=-1 do no Vshifts this phase, clear VSFLAG

= 1 do one Vshift, set WC6 bit-0 in WC6 mask and write it

out, then set VSFLAG

>= 2 load NVSHIFTnext into the N.V.SHIFT counter, issue a

load command then #step the counter, set WC6 bit-1 in WC6

mask and write it out, and set VSFLAG

# to make the count equal to that resulting from a hardware TC load from the

hold register plus one count from the clock to end TC

- load the WC7 direction byte for the next phase, Pnext, by looking at

UPnext of Pnext's phase definition

if UPnext = 0 skip, ignore, don't change direction

= 1 shift up, forward or + direction, toward readout reg by

sending a WC7,1

=-1 shift down, reverse or - direction, away from RO reg by

sending a WC7,REVERSE, where REVERSE is as determined in the set-up sequence

- if BIASFLAG not set, and if this is a shuttered CSR, load EXPTM and/or

determine if shutter is to open in next phase

if EXPTMnext >= 2 load EXPTMnext into EXPTM counter load register and

set the SHUTTER_OPEN flag

= 1 disable shutter opening this phase by clearing the

SHUTTER_OPEN flag

= 0 set the SHUTTER_OPEN flag (this will repeat the already

loaded EXPTM)

- if BIASFLAG is set, and if this is a shuttered CSR, load value 2 into

EXPTM and set SHUTTER_OPEN flag

- determine if EXT is to change state in next phase

if ACTIRnext = 0 no action, skip leaving ACTIONFLAG clear

=-1 enable trigger EXT device, set EXTFLAG and ACTIONFLAG

= 1 open shutter set ACTIONFLAG (for non-shuttered open)

= 2 close shutter set ACTIONFLAG (for non-shuttered close)

 

- FORECAST FUTURE PHASE:

***FUTURE will be PNEXT+1 if PNEXTn has no REPEAT

or it will be PNEXT-OFFSET if PNEXTn has a REPEAT. This will start

another repeat unless the required number of repeats has been done in

which case FUTURE will be PNEXT+1

***if FUTURE has been set to PNEXT+1 do the CYCLETEST to determine if

PNEXT+1 is greater than PRnmax (the last running sequence PRn) indicating

the start of a new cycle may be required if the required number have not

already been done and the STOPFLAG is not set. Otherwise end-up sequence

or wrap-up is next and FUTURE will be set to PE1 or go straight to

wrap-up.

REFER TO: PSEUDO CODE FOR CHARGE SHUFFLING EXPOSURE RUNNING SEQUENCE - 18/9/95

LGW appended below, for further details of the microcode that actually

implements the running sequence.....

- is REPEATnext zero, indicating PNEXT is not a repeat pointing phase

- yes, indicating take next sequential phase in table

- set FUTURE=PNEXT+1 then go to CYCLETEST

- no, indicating that this is a repeat pointing phase

- is REPCNTR=0 (the repeat counter)

- yes, indicating that this is the first time this repeat

pointing phase has been encountered and is the start of

a new repeat seq

- load REPEATnext into REPCNTR

- set FUTURE=PNEXT-OFFSETnext and go to END

- no, indicating that this repeat pointing phase has been

encountered recently and that the repeat loop may not be

finished

- decrement REPCNTR

- is REPCNTR=0? test state of repeats

- yes, indicating imminent completion of repeats

- set FUTURE=PNEXT+1 then go to CYCLETEST

- no, indicating another repeat needed

- set FUTURE=PNEXT-OFFSETnext, go to END

- CYCLETEST: test if FUTURE>PH_NUM_MAX?

[PH_NUM_MIN loaded with PSnmin when in starting-sequence

PRnmin when in running-sequence

PEnmin when in end-sequence]

[PH_NUM_MAX loaded with PSnmax when in starting-sequence

PRnmax when in running-sequence

PEnmax when in end-sequence]

******** DOESNT WORK AT END OF RUNNING WITH PE1 AND PE2 ABOUT TO OR ALREADY IN

THE FUTURE REGISTER........

MAYBE DO THE CYCLETEST ONLY IF TESTING A PR AND NOT A PE???? *************

 

- no: indicating not close to the end of cycle

- go to END

- yes: indicating that end of cycle is imminent

- decrement SCC the cycle counter

- is SCC=0

- no: indicating another cycle should be started

- but is STOPFLAG set?

- yes, premature end of running sequence requested

- set FUTURE=PE1 or set FUTURE=0 if come to

the end of the phase table and go to END

- no , need to start the next cycle

- set FUTURE=PH_NUM_MIN and go to END

- yes: indicating that end of running sequence is imminent

- set FUTURE=PE1 or set FUTURE=0 if come to

the end of the phase table and go to END

- END... continue...

- a strobe on pin B12/R1 could be issued at the start of the wait for interrupt

in order to assess the spare time available.

- enable TEL. if possible. The uP could actually do its part of TEL at this

time without a VAX command (ie the part that reads the hardware and is

prohibited during normal ROM because it interferes with the readout) and keep

updating the results in its RAM. When the VAX asks for TEL the RAM values are

sent without doing the uP/hardware part of TEL.

*** NOT IN EXPERIMENTAL STAGE PERHAPS ***

- disable TEL just before I/R due

*** NOT IN EXPERIMENTAL STAGE PERHAPS ***

- jump back to [A] above

- END2:

- wait for next TINCR (or SYNC...) interrupt

- END3 immediately enter end-up sequence

 

 

 

 

END-UP SEQUENCE

***************

- end-up sequence status, xs = 4, sent to the VAX on demand

End-up sequence is entered during the processing of the phase definition table

after the phase start interrupt by one of two ways.

PNEXT may be set to PE1 (before the register shuffle) indicating that there is

at least one PE entry in the phase definition table to be executed in end-up

sequence using the same phase processing code as for the running sequence.

After the last PE line of the table is processed the code will set PNEXT to

zero and thus processing should go straight to the micro code below

Alternatively, PNEXT may already be set to zero on entering end-up sequence

indicating that no PE phase definitions exist in the table after the running

sequence and thus processing should go straight to the micro code below

- END status set here

- stop the TINCR counter, now that all PXn's have completed, by resetting the

GATE TINCR bit of the set/reset register

- test status_byte to determine if shutter is open.

- if so, do a further STOP EXP pulse to close shutter

- insert a 100ms wait loop before skipping to wrapup

- if not, skip to wrapup

 

 

WRAP-UP SEQUENCE

****************

- wrap-up status, xs = 5, sent to the VAX on demand

- clear EN FULL uP VSC bit in the set/reset byte. This will re-enable the

hardware retriggering of V shifts

- re-arm the XTRL/PPL counter and set its output low again.

- re-store to normal using the saved list of changed parameters saved prior to

run start the following

- C14 MMR

- C24 MMR

- TINCR CMR

- EXPTM CMR

- N.VS CNTR CMR

- WC1

- WC4

- WC6

- WC7

- the N.VS CNTR may need its alarm reg reloaded??

- reset the ENABLE CSR selective set/clear flip=flop, EN CSR, by writing to the

selective reset register SR 80. This prevents the generation of V clocks in the

WAITM condition returning the clock generation back to normal.

- get the loop going now that the controller is back in hardware control and

the normal parameters have been restored. Do this by saving WC6, writing WC6,01

(complete one V shift) followed by a TRIG VSHIFT pulse (this will start the

loop with the uPTPhiV pulse). Finally, restore WC6 with the saved value.

- issue a reset FIFO pulse

- return TEL to normal

- wrap-up complete status, xs = 0, sent to the VAX on demand

- await the VAX "ro" command to start the normal CCD readout as per speed and

window spec

 

 

 

 

 

COMPUTING THE CSR EXPOSURE TIMES

********************************

 

Started 29/9/95

Updated 3/10/95

J.R.Barton

ccd_charge_shuffling.txt

 

The total exposure time is the time from when the micro receives the cs command

to the time when the VAX is able to poll for status without interfering with

the timing of the CSR, i.e. the CSR should have completed and is ready for the

CCD readout.

The following VAX inputs are required:

1. Tsync-start for cs(n5) in seconds

2. PERIOD1 or 2 is the SYNC1 or 2 period (in seconds) needed if cs(n6) = 1 or

2 and should be entered by the astronomer to 6 dec places (i.e. 1us

precision)

The total exposure time comprises the sum of the following times (as relevent

to the type of CSR)

 

 

WAITING FOR A SYNC1/2 START

If cs(n5) = 0, Tsync-start = 0.001 sec, i.e. minimum delay to start

If cs(n5) = 1 or 2 then an estimate must be made of the time that will elapse

after issuing the cs command to when the SYNC1 or 2 exposure start interrupt

will be received. Here, Tsync-start may be up to a full period if these

interrupts oare periodical. Other wise they may occur at random or....

 

 

GETTING INTO SYNC

If cs(n6) = 3 (TINCR triggers all phases) then

Tget-in-sync= 0.040 sec

If cs(n6) = 1 or 2 then

Tget-in-sync= (from 1 to 2)*SYNC1/2 period, sec

 

 

START SEQUENCE RUN TIME

PSi=S PSm=i

Tstart-sequ = SIGMA (PHTIMEi + SIGMA (PHTIMEm * REPEATi))

PSi=1 PSm=(i-OFFSETi)

where PSi is the i-th start phase entry in the table starting at PS1 and

containing a total of S start phase entries

PSm are start phase entries involved in a repeat loop defined by the

phase entry PSi parameters REPEATi and OFFSETi.

If cs(n6) = 3 then

PHTIMEi/m = TINCRi / 10exp(6 - cs(n2)) secs

if cs(contr) = 0, 1, 2, or 3 (NP or DF)

or else PHTIMEi/m = TINCRmin / 10exp(6 - cs(n2)) secs

if cs(contr) = 4 or 6 (BF)

where TINCRmin = cs(n3)

If cs(n6) = 1 or 2 and indep of cs(contr)

PHTIMEi/m = PERIOD1 or 2

where PERIOD1/2 is the SYNC1/2 interrupt period (secs)

 

 

RUNNING SEQUENCE RUN TIME

PRi=R PRm=i

Trun-sequ = CYCLES * SIGMA (PHTIMEi + SIGMA (PHTIMEm * REPEATi))

PRi=1 PRm=(i-OFFSETi)

where PRi is the i-th run phase entry in the table starting at PR1 and

containing a total of R run phase entries

PRm are run phase entries involved in a repeat loop defined by the

phase entry PRi parameters REPEATi and OFFSETi.

CYCLES is the number of run cycles given by cs(n1)

If cs(n6) = 3 then

PHTIMEi/m = TINCRi / 10exp(6 - cs(n2)) secs

if cs(contr) = 0, 1, 2, or 3 (NP or DF) or else

PHTIMEi/m = TINCRmin / 10exp(6 - cs(n2)) secs

if cs(contr) = 4 or 6 (BF)

where TINCRmin = cs(n3)

If cs(n6) = 1 or 2 and indep of cs(contr)

PHTIMEi/m = PERIOD1 or 2

where PERIOD1/2 is the SYNC1/2 interrupt period (secs)

 

 

END SEQUENCE RUN TIME

PEi=E PEm=i

Tend-sequ = SIGMA (PHTIMEi + SIGMA (PHTIMEm * REPEATi))

PEi=1 PEm=(i-OFFSETi)

where PEi is the i-th end phase entry in the table starting at PE1 and

containing a total of E end phase entries

PEm are end phase entries involved in a repeat loop defined by the

phase entry PEi parameters REPEATi and OFFSETi.

If cs(n6) = 3 then

PHTIMEi/m = TINCRi / 10exp(6 - cs(n2)) secs

if cs(contr) = 0, 1, 2, or 3 (NP or DF)

or else PHTIMEi/m = TINCRmin / 10exp(6 - cs(n2)) secs

if cs(contr) = 4 or 6 (BF)

where TINCRmin = cs(n3)

If cs(n6) = 1 or 2 and indep of cs(contr)

PHTIMEi/m = PERIOD1 or 2

where PERIOD1/2 is the SYNC1/2 interrupt period (secs)

 

 

SHORTENED TIMES DUE TO A PREMATURE STOP

When the CSR exposure is terminated prematurely the VAX should estimate as best

as possible when to start polling for status prior to initiating the CCD

readout. Premature stops occur either when the cs command is invoked or, when

cs(n7) is set to 1 or 2, by SYNC1/2 being used to stop the exposure and both

terminate the CSR after completing the current run cycle.

For the sc command, the VAX is able to delay the start of polling until a

further single run sequence cycle time plus end sequence run time has expired

after the sc command was issued. If the cycle time is very long, the VAX should

be able to improve on the estimated time to start polling by estimating how far

through the cycle the CSR has progressed at the time the sc command was sent.

The SYNC1/2 case presents a problem for the VAX if it does not know when these

SYNC stops will occur. Maybe those CSRs with cs(n7) set to 1 or 2 will need to

be polled right from the start.... or after an estimated delay.... or maybe the

VAX polling can be initiated from the keyboard as the observer will probably

know when the SYNC1/2 happens - this could be done as a manually initiated

readout (the VAX first polling for status before initiating the readout.

 

SHORTENED TIMES DUE TO ABORTS

Once the ai command is issued the VAX may start polling the exposure status for

xs = 0, the idle state. The abort is recognised at the end of the current run

phase, the end sequence is skipped and the wrapup is done before the idle state

is set. Once xs = 0 is detected the VAX should issue an IN command.

___________________________________________________________________________

 

SYSTEM TESTS

************

FOR POCKET PUMPING

- One flash for EXPTM and lots of shuffles with closed shutter

- Flash between each shift. How does this compare with above

- Change clock voltages affect traps?

- trapped charge vs number of shifts

- trapped charge vs intensitiy for one flash and multi flash inputs above

- traps vs PTE setting

 

 

PSEUDO CODE FOR CHARGE SHUFFLING EXPOSURE RUNNING SEQUENCE - 18/9/95 LGW

*************************************************************************

On Receipt of 'PT' command ...

Calculate Total Number of Start Phases to be Executed

Calculate Total Number of Run Phases to be Executed

Calculate Total Number of End Phases to be Executed

Using the formula:

Total X Phases = Sigma (((1 + X Phase i Repeats) x (1 + X Phase i Offset)) - X

Phase i Offset))

i = 1 to Number of X Phase Entries

X = Start, Run, End

 

On Receipt of 'cs' command (which specifies Cycles)

Total Phases to Execute = Total Start Phases to Execute +

Total Run Phases to Execute x Cycles +

Total End Phases to Execute

The following pseudo code describes execution of the Running Sequence in

Charge Shuffling Exposure Mode.

Set Running Status (xs == 2)

if cs_Start_Phase_Trigger = TINCR then

Kick Start TINCR

Wait for Phase Sync Interrupt

Cycle Count = Cycles

Next Phase = First Phase Entry

Offset Phase Count = 0

Phase Repeat Count = Next Phase Repeat Count

if Next Phase == Last Run Phase and Cycle Count > 1 then

begin

Future Phase = First Run Phase

Cycle Count = Cycle Count - 1

end

else

begin

Future Phase = Next Phase + 1

end

 

Wait for First Phase Sync Interrupt

while Total Phases to Execute > 0 and Abort Flag False

begin

Current Phase = Next Phase

Next Phase = Future Phase

Execute Current Phase

Setup Next Phase

if Phase Repeat Count == 0 then

begin

if Next Phase Offset > 0 then

begin

Offset Phase Count = Next Phase Offset + 1

Phase Repeat Count = Next Phase Repeat Count

Future Phase = Next Phase - Next Phase Offset

end

else {Next Phase Offset == 0}

begin

if Next Phase Repeat Count > 0 then

begin

Phase Repeat Count = Next Phase Repeat Count

Offset Phase Count = 0

Future Phase = Next Phase

end

else

begin

Phase Repeat Count = 0

Offset Phase Count = 0

if Next Phase == Last Run Phase and Cycle Count > 1 then

begin

Future Phase = First Run Phase

Cycle Count = Cycle Count - 1

end

else

begin

Future Phase = Next Phase + 1

end

end

end

end

else {Phase Repeat Count > 0}

begin

if Offset Phase Count > 0 then

begin

Offset Phase Count = Offset Phase Count - 1

if Offset Phase Count == 0 then

begin

Phase Repeat Count = Phase Repeat Count - 1

if Phase Repeat Count == 0 then

begin

if Next Phase == Last Run Phase and Cycle Count > 1 then

begin

Future Phase = First Run Phase

Cycle Count = Cycle Count - 1

end

else

begin

Future Phase = Next Phase + 1

end

end

else

begin

Future Phase = Next Phase - Next Phase Offset

Phase Count = Next Phase Offset + 1

end

end

else

begin

if Next Phase == Last Run Phase and Cycle Count > 1 then

begin

Future Phase = First Run Phase

Cycle Count = Cycle Count - 1

end

else

begin

Future Phase = Next Phase + 1

end

end

end

else

begin

Phase Repeat Count = Phase Repeat Count - 1

if Phase Repeat Count == 0 then

begin

if Next Phase == Last Run Phase and Cycle Count > 1 then

begin

Future Phase = First Run Phase

Cycle Count = Cycle Count - 1

end

else

begin

Future Phase = Next Phase + 1

end

end

else

begin

Future Phase = Next Phase

end

end

end

Total Phases To Execute = Total Phases To Execute - 1

Test External Sync Input

if Stop At End of Cycle Flag True then

begin

Reset Stop At End of Cycle Flag

if Cycle Count > 1 then

begin

if Total Phases to Execute > (Total Run Phases to Execute x Cycles + Total End Phases To Execute) then

begin

Total Phases To Execute = Total End Phases to Execute - Total Run Phases To Execute x (Cycles - 1)

Cycle Count = 1

end

else if Total Phases To Execute > Total End Phases To Execute then

begin

Total Phases To Execute = Total End Phases to Execute - Total Run Phases To Execute x (Cycle Count - 1)

Cycle Count = 1

end

end

end

Wait for Next Phase Sync Interrupt

end